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| data sheet, v1.0, nov. 2003 microcontrollers never stop thinking. c161s 16-bit single-chip microcontroller
edition 2003-11 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. data sheet, v1.0, nov. 2003 microcontrollers never stop thinking. c161s 16-bit single-chip microcontroller template: mc_tmplt_a5.fm / 3 / 2003-09-01 c161s revision history: 2003-11 v1.0 previous version: none page subjects (major changes since last revision) we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com c161s 16-bit single-chip microcontroller c166 family c161s data sheet 1 v1.0, 2003-11 1 summary of features ? high performance 16-bit cpu with 4-stage pipeline ? 80 ns instruction cycle time at 25 mhz cpu clock ? 400 ns multiplication (16 16 bit), 800 ns division (32 / 16 bit) ? enhanced boolean bit manipulation facilities ? additional instructions to support hll and operating systems ? register-based design with multiple variable register banks ? single-cycle context switching support ? 16 mbytes total linear address space for code and data ? 1024 bytes on-chip special function register area 16-priority-level interrupt system with 30 sources, sample-rate down to 40 ns 8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller (pec) clock generation via on-chip pll (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input on-chip memory modules: 2 kbytes on-chip internal ram (iram) on-chip peripheral modules ? two multi-functional general purpose timer units with 5 timers ? two serial channels (sync./asynchronous and high-speed-synchronous) ? on-chip real time clock external address space for code and data ? programmable external bus characteristics for different address ranges ? multiplexed or demultiplexed external address/data buses with 8-bit or 16-bit data bus width ? four programmable chip-select signals ? 4 mbytes maximum address window size, results in a total external address space of 16 mbytes, when all chip-select signal (address windows) are active idle and power down modes with flexible power management programmable watchdog timer and oscillator watchdog up to 63 general purpose i/o lines, partly with selectable input thresholds and hysteresis power supply: the c161s can operate from a 5 v or a 3 v power supply (see table 1 ) supported by a large range of development tools like c-compilers, macro-assembler packages, emulators, evaluation boards, hll-debuggers, simulators, logic analyzer disassemblers, programming boards on-chip bootstrap loader 80-pin mqfp package c161s summary of features data sheet 2 v1.0, 2003-11 this document describes several derivatives of the c161 group. table 1 enumerates these derivatives and summarizes the differences. as this document refers to all of these derivatives, some descriptions may not apply to a specific product. for simplicity all versions are referred to by the term c161s throughout this document. ordering information the ordering code for infineon microcontrollers provides an exact reference to the required product. this ordering code identifies: the derivative itself, i.e. its function set, the temperature range, and the supply voltage the package and the type of delivery. for the available ordering codes for the c161s please refer to the ?product catalog microcontrollers? , which summarizes all available microcontroller variants. note: the ordering codes for mask-rom versions are defined for each product after verification of the respective rom code. table 1 c161s derivative synopsis derivative max. operating frequency operating voltage ambient temperature sab-c161s-l25m 25 mhz 4.5 to 5.5 v (standard) 0 to 70 c saf-c161s-l25m 25 mhz 4.5 to 5.5 v (standard) -40 to 85 c sab-c161s-lm3v 20 mhz 3.0 to 3.6 v (reduced) 0 to 70 c saf-c161s-lm3v 20 mhz 3.0 to 3.6 v (reduced) -40 to 85 c c161s general device information data sheet 3 v1.0, 2003-11 2 general device information 2.1 introduction the c161s is a derivative of the infineon c166 family of full featured single-chip cmos microcontrollers. it combines high cpu performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced io-capabilities. it also provides clock generation via pll and power management features. the c161s is especially suited for cost sensitive applications. figure 1 logic symbol mca05504 c161s xtal1 xtal2 rstin rstout nmi ea ale rd wr/wrl port 5 2 bit port 6 4 bit port 4 6 bit port 3 12 bit port 2 7 bit port1 16 bit port0 16 bit v dd v ss c161s general device information data sheet 4 v1.0, 2003-11 2.2 pin configuration and definition figure 2 pin configuration (top view) p4.1/a17 p4.0/a16 p3.13/sclk p3.12/bhe/wrh p3.11/rxd0 p3.10/txd0 p3.9/mtsr p3.8/mrst p3.7/t2in p3.6/t3in p3.5/t4in p3.4/t3eud xtal2 xtal1 v ss v dd p3.2/capin p3.3/t3out p4.2/a18 p4.3/a19 c161s p0h.1/ad9 v ss v dd p4.4/a20 p4.5/a21 ale ea p0l.0/ad0 p0l.1/ad1 p0l.4/ad4 p0l.5/ad5 p0l.6/ad6 p0l.7/ad7 p0h.0/ad8 rd wr/wrl p0l.2/ad2 p0l.3/ad3 v dd v ss p0h.3/ad11 p0h.4/ad12 p0h.5/ad13 p0h.6/ad14 p0h.7/ad15 p1l.0/a0 p1l.1/a1 p1l.2/a2 p1l.3/a3 p1l.4/a4 p1l.5/a5 p1l.6/a6 p1l.7/a7 p1h.2/a10 p1h.3/a11 p1h.4/a12 p1h.5/a13 p0h.2/ad10 p1h.0/a8 p1h.1/a9 p5.15/t2eud p5.14/t4eud p2.15/ex7in p2.14/ex6in p2.13/ex5in p2.11/ex3in p2.10/ex2in p6.2/cs2 p6.1/cs1 p6.0/cs0 nmi rstout rstin v ss p1h.6/a14 p1h.7/a15 v dd p6.3/cs3 p2.9/ex1in p2.12/ex4in mcp05505 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 160 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 c161s general device information data sheet 5 v1.0, 2003-11 table 2 pin definitions and functions symbol pin no. input outp. function xtal1 xtal2 2 3 i o xtal1: input to the oscillator amplifier and input to the internal clock generator xtal2: output of the oscillator amplifier circuit. to clock the device from an external source, drive xtal1, while leaving xtal2 unconnected. minimum and maximum high/low and rise/fall times specified in the ac characteristics (see chapter 5.4 ) must be observed. p3 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p3.8 p3.9 p3.10 p3.11 p3.12 p3.13 5 6 7 8 9 10 11 12 13 14 15 16 io i o i i i i i/o i/o o i/o o o i/o port 3 is a 12-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. port 3 outputs can be configured as push/pull or open drain drivers. the following port 3 pins also serve for alternate functions: capin gpt2 register caprel capture input t3out gpt1 timer t3 toggle latch output t3eud gpt1 timer t3 external up/down control input t4in gpt1 timer t4 count/gate/reload/capture inp. t3in gpt1 timer t3 count/gate input t2in gpt1 timer t2 count/gate/reload/capture inp. mrst ssc master-receive/slave-transmit inp./outp. mtsr ssc master-transmit/slave-receive outp./inp. txd0 asc0 clock/data output (async./sync.) rxd0 asc0 data input (async.) or inp./outp. (sync.) bhe external memory high byte enable signal, wrh external memory high byte write strobe sclk ssc master clock output / slave clock input. p4 p4.0 p4.1 p4.2 p4.3 p4.4 p4.5 17 18 19 20 23 24 io o o o o o o port 4 is a 6-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. port 4 can be used to output the segment address lines: a16 least significant segment address line a17 segment address line a18 segment address line a19 segment address line a20 segment address line a21 segment address line c161s general device information data sheet 6 v1.0, 2003-11 rd 25 o external memory read strobe. rd is activated for every external instruction or data read access. wr / wrl 26 o external memory write strobe. in wr -mode this pin is activated for every external data write access. in wrl -mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. see wrcfg in register syscon for mode selection. ale 27 o address latch enable output. can be used for latching the address into external memory or an address latch in the multiplexed bus modes. ea 28 i external access enable pin. a low level at this pin during and after reset forces the c161s to begin instruction execution out of external memory. a high level forces execution out of the internal program memory. ?romless? versions must have this pin tied to ?0?. port0 p0l.0-7 p0h.0-7 29-36 39-46 io port0 consists of the two 8-bit bidirectional i/o ports p0l and p0h. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. in case of an external bus configuration, port0 serves as the address (a) and address/data (ad) bus in multiplexed bus modes and as the data (d) bus in demultiplexed bus modes. demultiplexed bus modes: data path width: 8-bit 16-bit p0l.0 ? p0l.7: d0 ? d7 d0 ? d7 p0h.0 ? p0h.7: i/o d8 ? d15 multiplexed bus modes: data path width: 8-bit 16-bit p0l.0 ? p0l.7: ad0 ? ad7 ad0 ? ad7 p0h.0 ? p0h.7: a8 ? a15 ad8 ? ad15 table 2 pin definitions and functions (cont?d) symbol pin no. input outp. function c161s general device information data sheet 7 v1.0, 2003-11 port1 p1l.0-7 p1h.0-7 47-54 55-62 io port1 consists of the two 8-bit bidirectional i/o ports p1l and p1h. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high-impedance state. port1 is used as the 16-bit address bus (a) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. rstin 65 i/o reset input with schmitt-trigger characteristics. a low level at this pin while the oscillator is running resets the c161s. an internal pull-up resistor permits power-on reset using only a capacitor connected to v ss . a spike filter suppresses input pulses < 10 ns. input pulses > 100 ns safely pass the filter. the minimum duration for a safe recognition should be 100 ns + 2 cpu clock cycles. in bidirectional reset mode (enabled by setting bit bdrsten in register syscon) the rstin line is internally pulled low for the duration of the internal reset sequence upon any reset (hw, sw, wdt). see note below this table. note: to let the reset configuration of port0 settle and to let the pll lock a reset duration of approx. 1 ms is recommended. rst out 66 o internal reset indication output. this pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. rstout remains low until the einit (end of initialization) instruction is executed. nmi 67 i non-maskable interrupt input. a high to low transition at this pin causes the cpu to vector to the nmi trap routine. when the pwrdn (power down) instruction is executed, the nmi pin must be low in order to force the c161s to go into power down mode. if nmi is high, when pwrdn is executed, the part will continue to run in normal mode. if not used, pin nmi should be pulled high externally. table 2 pin definitions and functions (cont?d) symbol pin no. input outp. function c161s general device information data sheet 8 v1.0, 2003-11 p6 p6.0 p6.1 p6.2 p6.3 68 69 70 71 io o o o o port 6 is a 4-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. port 6 outputs can be configured as push/pull or open drain drivers. the port 6 pins also serve for alternate functions: cs0 chip select 0 output cs1 chip select 1 output cs2 chip select 2 output cs3 chip select 3 output p2 p2.9 p2.10 p2.11 p2.12 p2.13 p2.14 p2.15 72 73 74 75 76 77 78 io i i i i i i i port 2 is a 7-bit bidirectional i/o port. it is bit-wise programmable for input or output via direction bits. for a pin configured as input, the output driver is put into high- impedance state. port 2 outputs can be configured as push/pull or open drain drivers. the following port 2 pins also serve for alternate functions: ex1in fast external interrupt 1 input ex2in fast external interrupt 2 input ex3in fast external interrupt 3 input ex4in fast external interrupt 4 input ex5in fast external interrupt 5 input ex6in fast external interrupt 6 input ex7in fast external interrupt 7 input p5 p5.14 p5.15 79 80 i i i port 5 is a 2-bit input-only port with schmitt-trigger char. the pins of port 5 also serve as timer inputs: t4eud gpt1 timer t4 ext. up/down ctrl. input t2eud gpt1 timer t5 ext. up/down ctrl. input v dd 4, 22, 37, 64 ? digital supply voltage: + 5 v during normal operation and idle mode. + 3.3 v during reduced supply operation and idle mode. 2.5 v during power down mode. note: please refer to the operating conditions parameters. v ss 1, 21, 38, 63 ? digital ground. table 2 pin definitions and functions (cont?d) symbol pin no. input outp. function c161s general device information data sheet 9 v1.0, 2003-11 note: the following behavioural differences must be observed when the bidirectional reset is active: bit bdrsten in register syscon cannot be changed after einit and is cleared automatically after a reset. the reset indication flags always indicate a long hardware reset. the port0 configuration is treated like on a hardware reset. especially the bootstrap loader may be activated when p0l.4 is low. pin rstin may only be connected to external reset devices with an open drain output driver. a short hardware reset is extended to the duration of the internal reset sequence. c161s functional description data sheet 10 v1.0, 2003-11 3 functional description the architecture of the c161s combines advantages of both risc and cisc processors and of advanced peripheral subsystems in a very well-balanced way. in addition the on- chip memory blocks allow the design of compact systems with maximum performance. figure 3 gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the c161s. note: all time specifications refer to a cpu clock of 20 mhz (see definition in the ac characteristics section). figure 3 block diagram the program memory, the internal ram (iram) and the set of generic peripherals are connected to the cpu via separate buses. a fourth bus, the xbus, connects external resources as well as additional on-chip resources, the x-peripherals (see figure 3 ). c166-core cpu port 2 interrupt bus xtal mcb04323_1s.vsd osc / pll rtc wdt 32 16 interrupt controller 16-level priority pec external instr. / data gpt t2 t3 t4 t5 t6 ssc brgen (spi) asc0 brgen (usart) ebc xbus control external bus control iram dual port internal ram 2 kbytes progmem internal rom area data data 16 16 16 instr. / data port 0 port 6 6 4 port 1 16 2 16 port 5 port 3 12 port 4 7 peripheral data bus 16 on-chip xbus (16-bit demux) c161s functional description data sheet 11 v1.0, 2003-11 3.1 memory organization the memory space of the c161s is configured in a von neumann architecture which means that code memory, data memory, registers and i/o ports are organized within the same linear address space which includes 16 mbytes. the entire memory space can be accessed bytewise or wordwise. particular portions of the on-chip memory have additionally been made directly bitaddressable. the c161s is prepared to incorporate on-chip program memory (not in the rom-less derivatives, of course) for code or constant data. the internal rom area can be mapped either to segment 0 or segment 1. 2 kbytes of on-chip internal ram (iram) are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. a register bank can consist of up to 16 wordwide (r0 to r15) and/or bytewide (rl0, rh0, ?, rl7, rh7) so-called general purpose registers (gprs). 1024 bytes (2 512 bytes) of the address space are reserved for the special function register areas (sfr space and esfr space). sfrs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. unused sfr addresses are reserved for future members of the c166 family. in order to meet the needs of designs where more memory is required than is provided on chip, up to 16 mbytes of external ram and/or rom can be connected to the microcontroller. the maximum contiguous external address space is 4 mbytes, i.e. this is the maximum address window size. using the chip-select lines (multiple windows) this results in a maximum usable external address space of 16 mbytes. c161s functional description data sheet 12 v1.0, 2003-11 3.2 external bus controller all of the external memory accesses are performed by a particular on-chip external bus controller (ebc). it can be programmed either to single chip mode when no external memory is required, or to one of four different external memory access modes, which are as follows: 16-/18-/20-/22-bit addresses, 16-bit data, demultiplexed 16-/18-/20-/22-bit addresses, 16-bit data, multiplexed 16-/18-/20-/22-bit addresses, 8-bit data, multiplexed 16-/18-/20-/22-bit addresses, 8-bit data, demultiplexed in the demultiplexed bus modes, addresses are output on port1 and data is input/output on port0 or p0l, respectively. in the multiplexed bus modes both addresses and data use port0 for input/output. important timing characteristics of the external bus interface (memory cycle time, memory tri-state time, length of ale and read write delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. in addition, up to 4 independent address windows may be defined (via register pairs addrselx / busconx) which control the access to different resources with different bus characteristics. these address windows are arranged hierarchically where buscon4 overrides buscon3 and buscon2 overrides buscon1. all accesses to locations not covered by these 4 address windows are controlled by buscon0. up to 4 external cs signals (3 windows plus default) can be generated in order to save external glue logic. the c161s offers the possibility to switch the cs outputs to an unlatched mode. in this mode the internal filter logic is switched off and the cs signals are directly generated from the address. the unlatched cs mode is enabled by setting cscfg (syscon.6). for applications which require less than 4 mbytes of external memory space, this address space can be restricted to 1 mbyte, 256 kbytes, or to 64 kbytes. in this case port 4 outputs four, two, or no address lines at all. it outputs all 6 address lines, if the full address width is used. c161s functional description data sheet 13 v1.0, 2003-11 3.3 central processing unit (cpu) the main core of the cpu consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (alu) and dedicated sfrs. additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. based on these hardware provisions, most of the c161s?s instructions can be executed in just one machine cycle which requires 100 ns at 20 mhz cpu clock. for example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. all multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. another pipeline optimization, the so-called ?jump cache?, allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. figure 4 cpu block diagram the cpu has a register context consisting of up to 16 wordwide gprs at its disposal. these 16 gprs are physically allocated within the on-chip ram area. a context pointer (cp) register determines the base address of the active register bank to be accessed by the cpu at any time. the number of register banks is only restricted by the available internal ram space. for easy parameter passing, a register bank may overlap others. mcb02147 cpu sp stkov stkun instr. reg. instr. ptr. exec. unit 4-stage pipeline mdh mdl psw syscon context ptr. mul/div-hw r15 r0 general purpose registers bit-mask gen barrel - shifter alu (16-bit) data page ptr. code seg. ptr. internal ram r15 r0 rom 16 16 32 buscon 0 buscon 1 buscon 2 buscon 3 buscon 4 addrsel 4 addrsel 3 addrsel 2 addrsel 1 c161s functional description data sheet 14 v1.0, 2003-11 a system stack of up to 1024 words is provided as a storage for temporary data. the system stack is allocated in the on-chip ram area, and it is accessed by the cpu via the stack pointer (sp) register. two separate sfrs, stkov and stkun, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. the high performance offered by the hardware implementation of the cpu can efficiently be utilized by a programmer via the highly efficient c161s instruction set which includes the following instruction classes: arithmetic instructions logical instructions boolean bit manipulation instructions compare and loop control instructions shift and rotate instructions prioritize instruction data movement instructions system stack instructions jump and call instructions return instructions system control instructions miscellaneous instructions the basic instruction length is either 2 or 4 bytes. possible operand types are bits, bytes and words. a variety of direct, indirect or immediate addressing modes are provided to specify the required operands. c161s functional description data sheet 15 v1.0, 2003-11 3.3.1 interrupt system with an interrupt response time within a range from just 5 to 12 cpu clocks (in case of internal program execution), the c161s is capable of reacting very fast to the occurrence of non-deterministic events. the architecture of the c161s supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. any of these interrupt requests can be programmed to being serviced by the interrupt controller or by the peripheral event controller (pec). in contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is ?stolen? from the current cpu activity to perform a pec service. a pec service implies a single byte or word data transfer between any two memory locations with an additional increment of either the pec source or the destination pointer. an individual pec transfer counter is implicitly decremented for each pec service except when performing in the continuous transfer mode. when this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. pec services are very well suited, for example, for supporting the transmission or reception of blocks of data. the c161s has 8 pec channels each of which offers such fast interrupt-driven data transfer capabilities. a separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. via its related register, each source can be programmed to one of sixteen interrupt priority levels. once having been accepted by the cpu, an interrupt service can only be interrupted by a higher prioritized service request. for the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. fast external interrupt inputs are provided to service external interrupts with high precision requirements. these fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). software interrupts are supported by means of the ?trap? instruction in combination with an individual trap (interrupt) number. table 3 shows all of the possible c161s interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. note: interrupt nodes which are not used by associated peripherals, may be used to generate software controlled interrupt requests by setting the respective interrupt request bit (xir). c161s functional description data sheet 16 v1.0, 2003-11 table 3 c161s interrupt nodes source of interrupt or pec service request request flag enable flag interrupt vector vector location trap number unassigned node cc8ir cc8ie cc8int 00?0060 h 18 h external interrupt 1 cc9ir cc9ie cc9int 00?0064 h 19 h external interrupt 2 cc10ir cc10ie cc10int 00?0068 h 1a h external interrupt 3 cc11ir cc11ie cc11int 00?006c h 1b h external interrupt 4 cc12ir cc12ie cc12int 00?0070 h 1c h external interrupt 5 cc13ir cc13ie cc13int 00?0074 h 1d h external interrupt 6 cc14ir cc14ie cc14int 00?0078 h 1e h external interrupt 7 cc15ir cc15ie cc15int 00?007c h 1f h gpt1 timer 2 t2ir t2ie t2int 00?0088 h 22 h gpt1 timer 3 t3ir t3ie t3int 00?008c h 23 h gpt1 timer 4 t4ir t4ie t4int 00?0090 h 24 h gpt2 timer 5 t5ir t5ie t5int 00?0094 h 25 h gpt2 timer 6 t6ir t6ie t6int 00?0098 h 26 h gpt2 caprel reg. crir crie crint 00?009c h 27 h unassigned node adcir adcie adcint 00?00a0 h 28 h unassigned node adeir adeie adeint 00?00a4 h 29 h asc0 transmit s0tir s0tie s0tint 00?00a8 h 2a h asc0 transmit buffer s0tbir s0tbie s0tbint 00?011c h 47 h asc0 receive s0rir s0rie s0rint 00?00ac h 2b h asc0 error s0eir s0eie s0eint 00?00b0 h 2c h ssc transmit sctir sctie sctint 00?00b4 h 2d h ssc receive scrir scrie scrint 00?00b8 h 2e h ssc error sceir sceie sceint 00?00bc h 2f h unassigned node xp0ir xp0ie xp0int 00?0100 h 40 h unassigned node xp1ir xp1ie xp1int 00?0104 h 41 h unassigned node xp2ir xp2ie xp2int 00?0108 h 42 h pll/owd and rtc xp3ir xp3ie xp3int 00?010c h 43 h unassigned node cc29ir cc29ie cc29int 00?0110 h 44 h unassigned node cc30ir cc30ie cc30int 00?0114 h 45 h unassigned node cc31ir cc31ie cc31int 00?0118 h 46 h c161s functional description data sheet 17 v1.0, 2003-11 the c161s also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ?hardware traps?. hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). the occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (tfr). except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. in turn, hardware trap services can normally not be interrupted by standard or pec interrupts. table 4 shows all of the possible exceptions or error conditions that can arise during run- time: table 4 hardware trap summary exception condition trap flag trap vector vector location trap number trap priority reset functions: hardware reset software reset w-dog timer overflow ? reset reset reset 00?0000 h 00?0000 h 00?0000 h 00 h 00 h 00 h iii iii iii class a hardware traps: non-maskable interrupt stack overflow stack underflow nmi stkof stkuf nmitrap stotrap stutrap 00?0008 h 00?0010 h 00?0018 h 02 h 04 h 06 h ii ii ii class b hardware traps: undefined opcode protected instruction fault illegal word operand access illegal instruction access illegal external bus access undopc prtflt illopa illina illbus btrap btrap btrap btrap btrap 00?0028 h 00?0028 h 00?0028 h 00?0028 h 00?0028 h 0a h 0a h 0a h 0a h 0a h i i i i i reserved ? ? [2c h ? 3c h ] [0b h ? 0f h ] ? software traps trap instruction ?? any [00?0000 h ? 00?01fc h ] in steps of 4 h any [00 h ? 7f h ] current cpu priority c161s functional description data sheet 18 v1.0, 2003-11 3.4 general purpose timer (gpt) unit the gpt unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. the gpt unit incorporates five 16-bit timers which are organized in two separate modules, gpt1 and gpt2. each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. each of the three timers t2, t3, t4 of module gpt1 can be configured individually for one of four basic modes of operation, which are timer, gated timer, counter, and incremental interface mode. in timer mode, the input clock for a timer is derived from the cpu clock, divided by a programmable prescaler, while counter mode allows a timer to be clocked in reference to external events. pulse width or duty cycle measurement is supported in gated timer mode, where the operation of a timer is controlled by the ?gate? level on an external input pin. for these purposes, each timer has one associated port pin (txin) which serves as gate or clock input. the maximum resolution of the timers in module gpt1 is 16 tcl. the count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (txeud) to facilitate e.g. position tracking. in incremental interface mode the gpt1 timers (t2, t3, t4) can be directly connected to the incremental position sensor signals a and b via their respective inputs txin and txeud. direction and count signals are internally derived from these two input signals, so the contents of the respective timer tx corresponds to the sensor position. the third position sensor signal top0 can be connected to an interrupt input. timer t3 has an output toggle latch (t3otl) which changes its state on each timer over- flow/underflow. the state of this latch may be output on pin t3out e.g. for time out monitoring of external hardware components, or may be used internally to clock timers t2 and t4 for measuring long time periods with high resolution. in addition to their basic operating modes, timers t2 and t4 may be configured as reload or capture registers for timer t3. when used as capture or reload registers, timers t2 and t4 are stopped. the contents of timer t3 is captured into t2 or t4 in response to a signal at their associated input pins (txin). timer t3 is reloaded with the contents of t2 or t4 triggered either by an external signal or by a selectable state transition of its toggle latch t3otl. when both t2 and t4 are configured to alternately reload t3 on opposite state transitions of t3otl with the low and high times of a pwm signal, this signal can be constantly generated without software intervention. c161s functional description data sheet 19 v1.0, 2003-11 figure 5 block diagram of gpt1 with its maximum resolution of 8 tcl, the gpt2 module provides precise event control and time measurement. it includes two timers (t5, t6) and a capture/reload register (caprel). both timers can be clocked with an input clock which is derived from the cpu clock. the count direction (up/down) for each timer is programmable by software. concatenation of the timers is supported via the output toggle latch (t6otl) of timer t6, which changes its state on each timer overflow/underflow. the state of this latch may be used to clock timer t5. the overflows/underflows of timer t6 can cause a reload from the caprel register. the caprel register may capture the contents of timer t5 based on an external signal transition on the corresponding port pin (capin), and timer t5 may optionally be cleared after the capture procedure. this allows the c161s to measure absolute time differences or to perform pulse multiplication without software overhead. t3 mode control 2 n : 1 f cpu 2 n : 1 f cpu t2 mode control gpt1 timer t2 reload capture 2 n : 1 f cpu t4 mode control gpt1 timer t4 reload capture gpt1 timer t3 t3otl u/d t2eud t2in t3in t3eud t4in t4eud t3out toggle ff u/d u/d interrupt request interrupt request interrupt request other timers mct02141 n = 3 ? 10 c161s functional description data sheet 20 v1.0, 2003-11 the capture trigger (timer t5 to caprel) may also be generated upon transitions of gpt1 timer t3 ? s inputs t3in and/or t3eud. this is especially advantageous when t3 operates in incremental interface mode. figure 6 block diagram of gpt2 mux 2 n : 1 f sys t5 mode control gpt2 timer t5 2 n : 1 f sys t6 mode control gpt2 timer t6 gpt2 caprel t6otl t3in/ capin u/d u/d interrupt request (t5ir) interrupt request (crir) interrupt request (t6ir) clear capture ct3 mcb03999_x1s.vsd toggle ff clear n = 2 ? 9 c161s functional description data sheet 21 v1.0, 2003-11 3.5 real time clock the real time clock (rtc) module of the c161s consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer t14, and the 32-bit rtc timer (accessible via registers rtch and rtcl). the rtc module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver ( f rtc = f osc /32) and is therefore independent from the selected clock generation mode of the c161s. all timers count up. the rtc module can be used for different purposes: system clock to determine the current time and date cyclic time based interrupt 48-bit timer for long term measurements figure 7 rtc block diagram note: the registers associated with the rtc are not affected by a reset in order to maintain the correct system time even when intermediate resets are executed. mcd04432 t14rel t14 8:1 rtc f rtcl rtch interrupt request reload c161s functional description data sheet 22 v1.0, 2003-11 3.6 serial channels serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an asynchronous/synchronous serial channel ( asc0 ) and a high-speed synchronous serial channel ( ssc ). the asc0 is upward compatible with the serial ports of the infineon 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 625 kbit/s and half-duplex synchronous communication at up to 2.5 mbit/s (@ 20 mhz cpu clock). a dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. for transmission, reception and error handling 4 separate interrupt vectors are provided. in asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. for multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake-up bit mode). in synchronous mode, the asc0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the asc0. the asc0 always shifts the lsb first. a loop back option is available for testing purposes. a number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. a parity bit can automatically be generated on transmission or be checked on reception. framing error detection allows to recognize data frames with missing stop bits. an overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. the ssc supports full-duplex synchronous communication at up to 5 mbit/s (@ 20 mhz cpu clock). it may be configured so it interfaces with serially linked peripheral components. a dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. for transmission, reception, and error handling three separate interrupt vectors are provided. the ssc transmits or receives characters of 2 ? 16 bits length synchronously to a shift clock which can be generated by the ssc (master mode) or by an external master (slave mode). the ssc can start shifting with the lsb or with the msb and allows the selection of shifting and latching clock edges as well as the clock polarity. a number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. transmit and receive error supervise the correct handling of the data buffer. phase and baudrate error detect incorrect serial data. c161s functional description data sheet 23 v1.0, 2003-11 3.7 watchdog timer the watchdog timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. the watchdog timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the einit (end of initialization) instruction has been executed. thus, the chip ? s start-up procedure is always monitored. the software has to be designed to service the watchdog timer before it overflows. if, due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset and pulls the rstout pin low in order to allow external hardware components to be reset. the watchdog timer is a 16-bit timer, clocked with the system clock divided by 2/128. the high byte of the watchdog timer register can be set to a prespecified reload value (stored in wdtrel) in order to allow further variation of the monitored time interval. each time it is serviced by the application software, the high byte of the watchdog timer is reloaded. thus, time intervals between 25 s and 420 ms can be monitored (@ 20 mhz). the default watchdog timer interval after reset is 6.55 ms (@ 20 mhz). 3.8 parallel ports the c161s provides up to 63 i/o lines which are organized into six input/output ports and one input port. all port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. the i/o ports are true bidirectional ports which are switched to high impedance state when configured as inputs. the output drivers of three i/o ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. during the internal reset, all port pins are configured as inputs. all port lines have programmable alternate input or output functions associated with them. all port lines that are not used for these alternate functions may be used as general purpose io lines. port0 and port1 may be used as address and data lines when accessing external memory, while port 4 outputs the additional segment address bits a21/19/17 ? a16 in systems where segmentation is enabled to access more than 64 kbytes of memory. port 6 provides optional chip select signals. port 3 includes alternate functions of timers, serial interfaces, and the optional bus control signal bhe . port 5 is used for timer control signals. c161s functional description data sheet 24 v1.0, 2003-11 3.9 oscillator watchdog the oscillator watchdog (owd) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). for this operation the pll provides a clock signal which is used to supervise transitions on the oscillator clock. this pll clock is independent from the xtal1 clock. when the expected oscillator clock transitions are missing the owd activates the pll unlock / owd interrupt node and supplies the cpu with the pll clock signal. under these circumstances the pll will oscillate with its basic frequency. in direct drive mode the pll base frequency is used directly ( f cpu = 2 ? 5 mhz). in prescaler mode the pll base frequency is divided by 2 ( f cpu = 1 ? 2.5 mhz). note: the cpu clock source is only switched back to the oscillator clock after a hardware reset. the oscillator watchdog can be disabled by setting bit owddis in register syscon. in this case (owddis = ? 1 ? ) the pll remains idle and provides no clock signal, while the cpu clock signal is derived directly from the oscillator clock or via prescaler or sdd. also no interrupt request will be generated in case of a missing oscillator clock. note: at the end of a reset bit owddis reflects the inverted level of pin rd at that time. thus the oscillator watchdog may also be disabled via hardware by (externally) pulling the rd line low upon a reset, similar to the standard reset configuration via port0. c161s functional description data sheet 25 v1.0, 2003-11 3.10 power management the c161s provides several means to control the power it consumes either at a given time or averaged over a certain timespan. three mechanisms can be used (partly in parallel): power saving modes switch the c161s into a special operating mode (control via instructions). idle mode stops the cpu while the peripherals can continue to operate. power down mode stops all clock signals and all operation (rtc may optionally continue running). clock generation management controls the distribution and the frequency of internal and external clock signals (control via register syscon2). slow down mode lets the c161s run at a cpu clock frequency of f osc / 1 ? 32 (half for prescaler operation) which drastically reduces the consumed power. the pll can be optionally disabled while operating in slow down mode. peripheral management permits temporary disabling of peripheral modules (control via register syscon3). each peripheral can separately be disabled/enabled. a group control option disables a major part of the peripheral set by setting one single bit. the on-chip rtc supports intermittent operation of the c161s by generating cyclic wake-up signals. this offers full performance to quickly react on action requests while the intermittent sleep phases greatly reduce the average power consumption of the system. c161s functional description data sheet 26 v1.0, 2003-11 3.11 instruction set summary table 5 lists the instructions of the c161s in a condensed way. the various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the ? c166 family instruction set manual ? . this document also provides a detailed description of each instruction. table 5 instruction set summary mnemonic description bytes add(b) add word (byte) operands 2 / 4 addc(b) add word (byte) operands with carry 2 / 4 sub(b) subtract word (byte) operands 2 / 4 subc(b) subtract word (byte) operands with carry 2 / 4 mul(u) (un)signed multiply direct gpr by direct gpr (16- 16-bit) 2 div(u) (un)signed divide register mdl by direct gpr (16-/16-bit) 2 divl(u) (un)signed long divide reg. md by direct gpr (32-/16-bit) 2 cpl(b) complement direct word (byte) gpr 2 neg(b) negate direct word (byte) gpr 2 and(b) bitwise and, (word/byte operands) 2 / 4 or(b) bitwise or, (word/byte operands) 2 / 4 xor(b) bitwise xor, (word/byte operands) 2 / 4 bclr clear direct bit 2 bset set direct bit 2 bmov(n) move (negated) direct bit to direct bit 4 band, bor, bxor and/or/xor direct bit with direct bit 4 bcmp compare direct bit to direct bit 4 bfldh/l bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data 4 cmp(b) compare word (byte) operands 2 / 4 cmpd1/2 compare word data to gpr and decrement gpr by 1/2 2 / 4 cmpi1/2 compare word data to gpr and increment gpr by 1/2 2 / 4 prior determine number of shift cycles to normalize direct word gpr and store result in direct word gpr 2 shl / shr shift left/right direct word gpr 2 rol / ror rotate left/right direct word gpr 2 ashr arithmetic (sign bit) shift right direct word gpr 2 c161s functional description data sheet 27 v1.0, 2003-11 mov(b) move word (byte) data 2 / 4 movbs move byte operand to word operand with sign extension 2 / 4 movbz move byte operand to word operand with zero extension 2 / 4 jmpa, jmpi, jmpr jump absolute/indirect/relative if condition is met 4 jmps jump absolute to a code segment 4 j(n)b jump relative if direct bit is (not) set 4 jbc jump relative and clear bit if direct bit is set 4 jnbs jump relative and set bit if direct bit is not set 4 calla, calli, callr call absolute/indirect/relative subroutine if condition is met 4 calls call absolute subroutine in any code segment 4 pcall push direct word register onto system stack and call absolute subroutine 4 trap call interrupt service routine via immediate trap number 2 push, pop push/pop direct word register onto/from system stack 2 scxt push direct word register onto system stack and update register with word operand 4 ret return from intra-segment subroutine 2 rets return from inter-segment subroutine 2 retp return from intra-segment subroutine and pop direct word register from system stack 2 reti return from interrupt service subroutine 2 srst software reset 4 idle enter idle mode 4 pwrdn enter power down mode (supposes nmi -pin being low) 4 srvwdt service watchdog timer 4 diswdt disable watchdog timer 4 einit signify end-of-initialization on rstout -pin 4 atomic begin atomic sequence 2 extr begin extended register sequence 2 extp(r) begin extended page (and register) sequence 2 / 4 exts(r) begin extended segment (and register) sequence 2 / 4 nop null operation 2 table 5 instruction set summary (cont ? d) mnemonic description bytes c161s functional description data sheet 28 v1.0, 2003-11 3.12 special function registers overview table 6 lists all sfrs which are implemented in the c161s in alphabetical order. the following markings assist in classifying the listed registers: ? b ? in the ? name ? column marks bit-addressable sfrs. ? e ? in the ? physical address ? column marks (e)sfrs in the extended sfr-space . ? x ? in the ? physical address ? column marks registers within on-chip x-peripherals. table 6 c161s registers, ordered by name name physical address 8-bit addr. description reset value adcic b ff98 h cc h software interrupt control register 0000 h addrsel1 fe18 h 0c h address select register 1 0000 h addrsel2 fe1a h 0d h address select register 2 0000 h addrsel3 fe1c h 0e h address select register 3 0000 h addrsel4 fe1e h 0f h address select register 4 0000 h adeic b ff9a h cd h software interrupt control register 0000 h buscon0 b ff0c h 86 h bus configuration register 0 0xx0 h buscon1 b ff14 h 8a h bus configuration register 1 0000 h buscon2 b ff16 h 8b h bus configuration register 2 0000 h buscon3 b ff18 h 8c h bus configuration register 3 0000 h buscon4 b ff1a h 8d h bus configuration register 4 0000 h caprel fe4a h 25 h gpt2 capture/reload register 0000 h cc10ic b ff8c h c6 h ex2in interrupt control register 0000 h cc11ic b ff8e h c7 h ex3in interrupt control register 0000 h cc12ic b ff90 h c8 h ex4in interrupt control register 0000 h cc13ic b ff92 h c9 h ex5in interrupt control register 0000 h cc14ic b ff94 h ca h ex6in interrupt control register 0000 h cc15ic b ff96 h cb h ex7in interrupt control register 0000 h cc29ic b f184 h e c2 h software interrupt control register 0000 h cc30ic b f18c h e c6 h software interrupt control register 0000 h cc31ic b f194 h e ca h software interrupt control register 0000 h cc8ic b ff88 h c4 h software interrupt control register 0000 h cc9ic b ff8a h c5 h ex1in interrupt control register 0000 h c161s functional description data sheet 29 v1.0, 2003-11 cp fe10 h 08 h cpu context pointer register fc00 h cric b ff6a h b5 h gpt2 caprel interrupt ctrl. reg. 0000 h csp fe08 h 04 h cpu code seg. pointer reg. (read only) 0000 h dp0h b f102 h e 81 h p0h direction control register 00 h dp0l b f100 h e 80 h p0l direction control register 00 h dp1h b f106 h e 83 h p1h direction control register 00 h dp1l b f104 h e 82 h p1l direction control register 00 h dp2 b ffc2 h e1 h port 2 direction control register 0000 h dp3 b ffc6 h e3 h port 3 direction control register 0000 h dp4 b ffca h e5 h port 4 direction control register 00 h dp6 b ffce h e7 h port 6 direction control register 00 h dpp0 fe00 h 00 h cpu data page pointer 0 reg. (10 bits) 0000 h dpp1 fe02 h 01 h cpu data page pointer 1 reg. (10 bits) 0001 h dpp2 fe04 h 02 h cpu data page pointer 2 reg. (10 bits) 0002 h dpp3 fe06 h 03 h cpu data page pointer 3 reg. (10 bits) 0003 h exicon b f1c0 h e e0 h external interrupt control register 0000 h idchip f07c h e 3e h identifier 05xx h idmanuf f07e h e 3f h identifier 1820 h idmem f07a h e 3d h identifier 0000 h idmem2 f076 h e 3b h identifier 0000 h idprog f078 h e 3c h identifier 0000 h isnc b f1de h e ef h interrupt subnode control register 0000 h mdc b ff0e h 87 h cpu multiply divide control register 0000 h mdh fe0c h 06 h cpu multiply divide reg. ? high word 0000 h mdl fe0e h 07 h cpu multiply divide reg. ? low word 0000 h odp2 b f1c2 h e e1 h port 2 open drain control register 0000 h odp3 b f1c6 h e e3 h port 3 open drain control register 0000 h odp6 b f1ce h e e7 h port 6 open drain control register 00 h ones b ff1e h 8f h constant value 1 ? s register (read only) ffff h p0h b ff02 h 81 h port 0 high reg. (upper half of port0) 00 h table 6 c161s registers, ordered by name (cont ? d) name physical address 8-bit addr. description reset value c161s functional description data sheet 30 v1.0, 2003-11 p0l b ff00 h 80 h port 0 low reg. (lower half of port0) 00 h p1h b ff06 h 83 h port 1 high reg. (upper half of port1) 00 h p1l b ff04 h 82 h port 1 low reg.(lower half of port1) 00 h p2 b ffc0 h e0 h port 2 register 0000 h p3 b ffc4 h e2 h port 3 register 0000 h p4 b ffc8 h e4 h port 4 register (8 bits) 00 h p5 b ffa2 h d1 h port 5 register (read only) xxxx h p6 b ffcc h e6 h port 6 register (8 bits) 00 h pecc0 fec0 h 60 h pec channel 0 control register 0000 h pecc1 fec2 h 61 h pec channel 1 control register 0000 h pecc2 fec4 h 62 h pec channel 2 control register 0000 h pecc3 fec6 h 63 h pec channel 3 control register 0000 h pecc4 fec8 h 64 h pec channel 4 control register 0000 h pecc5 feca h 65 h pec channel 5 control register 0000 h pecc6 fecc h 66 h pec channel 6 control register 0000 h pecc7 fece h 67 h pec channel 7 control register 0000 h psw b ff10 h 88 h cpu program status word 0000 h rp0h b f108 h e 84 h system startup config. reg. (rd. only) xx h rtch f0d6 h e 6b h rtc high register xxxx h rtcl f0d4 h e 6a h rtc low register xxxx h s0bg feb4 h 5a h serial channel 0 baud rate generator reload register 0000 h s0con b ffb0 h d8 h serial channel 0 control register 0000 h s0eic b ff70 h b8 h serial channel 0 error interrupt ctrl. reg 0000 h s0rbuf feb2 h 59 h serial channel 0 receive buffer reg. (read only) xx h s0ric b ff6e h b7 h serial channel 0 receive interrupt control register 0000 h s0tbic b f19c h e ce h serial channel 0 transmit buffer interrupt control register 0000 h table 6 c161s registers, ordered by name (cont ? d) name physical address 8-bit addr. description reset value c161s functional description data sheet 31 v1.0, 2003-11 s0tbuf feb0 h 58 h serial channel 0 transmit buffer register (write only) 00 h s0tic b ff6c h b6 h serial channel 0 transmit interrupt control register 0000 h sp fe12 h 09 h cpu system stack pointer register fc00 h sscbr f0b4 h e 5a h ssc baudrate register 0000 h ssccon b ffb2 h d9 h ssc control register 0000 h ssceic b ff76 h bb h ssc error interrupt control register 0000 h sscrb f0b2 h e 59 h ssc receive buffer xxxx h sscric b ff74 h ba h ssc receive interrupt control register 0000 h ssctb f0b0 h e 58 h ssc transmit buffer 0000 h ssctic b ff72 h b9 h ssc transmit interrupt control register 0000 h stkov fe14 h 0a h cpu stack overflow pointer register fa00 h stkun fe16 h 0b h cpu stack underflow pointer register fc00 h syscon b ff12 h 89 h cpu system configuration register 1) 0xx0 h syscon2 b f1d0 h e e8 h cpu system configuration register 2 0000 h syscon3 b f1d4 h e ea h cpu system configuration register 3 0000 h t14 f0d2 h e 69 h rtc timer 14 register xxxx h t14rel f0d0 h e 68 h rtc timer 14 reload register xxxx h t2 fe40 h 20 h gpt1 timer 2 register 0000 h t2con b ff40 h a0 h gpt1 timer 2 control register 0000 h t2ic b ff60 h b0 h gpt1 timer 2 interrupt control register 0000 h t3 fe42 h 21 h gpt1 timer 3 register 0000 h t3con b ff42 h a1 h gpt1 timer 3 control register 0000 h t3ic b ff62 h b1 h gpt1 timer 3 interrupt control register 0000 h t4 fe44 h 22 h gpt1 timer 4 register 0000 h t4con b ff44 h a2 h gpt1 timer 4 control register 0000 h t4ic b ff64 h b2 h gpt1 timer 4 interrupt control register 0000 h t5 fe46 h 23 h gpt2 timer 5 register 0000 h t5con b ff46 h a3 h gpt2 timer 5 control register 0000 h table 6 c161s registers, ordered by name (cont ? d) name physical address 8-bit addr. description reset value c161s functional description data sheet 32 v1.0, 2003-11 t5ic b ff66 h b3 h gpt2 timer 5 interrupt control register 0000 h t6 fe48 h 24 h gpt2 timer 6 register 0000 h t6con b ff48 h a4 h gpt2 timer 6 control register 0000 h t6ic b ff68 h b4 h gpt2 timer 6 interrupt control register 0000 h tfr b ffac h d6 h trap flag register 0000 h wdt feae h 57 h watchdog timer register (read only) 0000 h wdtcon b ffae h d7 h watchdog timer control register 2) 00xx h xp0ic b f186 h e c3 h software interrupt control register 0000 h xp1ic b f18e h e c7 h software interrupt control register 0000 h xp2ic b f196 h e cb h software interrupt control register 0000 h xp3ic b f19e h e cf h rtc/pll interrupt control register 0000 h zeros b ff1c h 8e h constant value 0 ? s register (read only) 0000 h 1) the system configuration is selected during reset. 2) the reset value depends on the indicated reset source. table 6 c161s registers, ordered by name (cont ? d) name physical address 8-bit addr. description reset value c161s electrical parameters data sheet 33 v1.0, 2003-11 4 electrical parameters 4.1 absolute maximum ratings note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v dd or v in < v ss ) the voltage on v dd pins with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. table 7 absolute maximum rating parameters parameter symbol limit values unit notes min. max. storage temperature t st -65 150 c ? junction temperature t j -40 150 c under bias voltage on v dd pins with respect to ground ( v ss ) v dd -0.5 6.5 v ? voltage on any pin with respect to ground ( v ss ) v in -0.5 v dd + 0.5 v ? input current on any pin during overload condition i ov -10 10 ma ? absolute sum of all input currents during overload condition | i ov | ? 100 ma ? power dissipation p diss ? 1.5 w ? c161s electrical parameters data sheet 34 v1.0, 2003-11 4.2 operating conditions the following operating conditions must not be exceeded in order to ensure correct operation of the c161s. all parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. table 8 operating condition parameters parameter symbol limit values unit notes min. max. standard digital supply voltage v dd 4.5 5.5 v active mode, f cpumax = 25 mhz 2.5 1) 1) output voltages and output currents will be reduced when v dd leaves the range defined for active mode. 5.5 v power down mode reduced digital supply voltage v dd 3.0 3.6 v active mode, f cpumax = 20 mhz 2.5 1) 3.6 v power down mode digital ground voltage v ss 0 v reference voltage overload current i ov ? 5 ma per pin 2)3) 2) overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. v ov > v dd + 0.5 v or v ov < v ss - 0.5 v). the absolute sum of input overload currents on all pins may not exceed 50 ma . the supply voltage must remain within the specified limits. proper operation is not guaranteed if overload conditions occur on functional pins such as xtal1, rd , wr , etc. 3) not subject to production test, verified by design/characterization. absolute sum of overload currents | i ov | ? 50 ma 3) external load capacitance c l ? 100 pf ? ambient temperature t a 070 c sab-c161s ? -40 85 c saf-c161s ? -40 125 c sak-c161s ? c161s electrical parameters data sheet 35 v1.0, 2003-11 4.3 parameter interpretation the parameters listed in the following partly represent the characteristics of the c161s and partly its demands on the system. to aid in interpreting the parameters right, when evaluating them for a design, they are marked in column ? symbol ? : cc ( c ontroller c haracteristics): the logic of the c161s will provide signals with the respective timing characteristics. sr ( s ystem r equirement): the external system must provide signals with the respective timing characteristics to the c161s. c161s electrical parameters data sheet 36 v1.0, 2003-11 4.4 dc parameters table 9 dc characteristics (standard supply voltage range) (operating conditions apply) 1) parameter symbol limit values unit test condition min. max. input low voltage (ttl, all except xtal1) v il sr -0.5 0.2 v dd - 0.1 v ? input low voltage xtal1 v il2 sr -0.5 0.3 v dd v ? input high voltage (ttl, all except rstin and xtal1) v ih sr 0.2 v dd + 0.9 v dd + 0.5 v ? input high voltage rstin (when operated as input) v ih1 sr 0.6 v dd v dd + 0.5 v ? input high voltage xtal1 v ih2 sr 0.7 v dd v dd + 0.5 v ? output low voltage (port0, port1, port 4, ale, rd , wr , bhe , rstout , rstin 2) ) v ol cc ? 0.45 v i ol = 2.4 ma output low voltage (all other outputs) v ol1 cc ? 0.45 v i ol = 1.6 ma output high voltage 3) (port0, port1, port 4, ale, rd , wr , bhe , rstout ) v oh cc 2.4 ? v i oh = -2.4 ma 0.9 v dd ? v i oh = -0.5 ma output high voltage 3) (all other outputs) v oh1 cc 2.4 ? v i oh = -1.6 ma 0.9 v dd ? v i oh = -0.5 ma input leakage current (port 5) i oz1 cc ? 200 na 0 v < v in < v dd input leakage current (all other) i oz2 cc ? 500 na 0.45 v < v in < v dd rstin inactive current 4) i rsth 5) ? -10 a v in = v ih1 rstin active current 4) i rstl 6) -100 ? a v in = v il rd /wr inactive current 7) i rwh 5) ? -40 a v out = 2.4 v rd /wr active current 7) i rwl 6) -500 ? a v out = v olmax ale inactive current 7) i alel 5) ? 40 a v out = v olmax ale active current 7) i aleh 6) 500 ? a v out = 2.4 v port 6 inactive current 7) i p6h 5) ? -40 a v out = 2.4 v c161s electrical parameters data sheet 37 v1.0, 2003-11 port 6 active current 7) i p6l 6) -500 ? a v out = v ol1max port0 configuration current 7) i p0h 5) ? -10 a v in = v ihmin i p0l 6) -100 ? a v in = v ilmax xtal1 input current i il cc ? 20 a0 v < v in < v dd pin capacitance 8) (digital inputs/outputs) c io cc ? 10 pf f = 1 mhz, t a = 25 c 1) keeping signal levels within the levels specified in this table, ensures operation without overload conditions. for signal levels outside these specifications also refer to the specification of the overload current i ov . 2) valid in bidirectional reset mode only. 3) this specification is not valid for outputs which are switched to open drain mode. in this case the respective output will float and the voltage results from the external circuitry. 4) these parameters describe the rstin pull-up, which equals a resistance of ca. 50 to 250 k ? . 5) the maximum current may be drawn while the respective signal line remains inactive. 6) the minimum current must be drawn in order to drive the respective signal line active. 7) this specification is only valid during reset and adapt mode. 8) not subject to production test, verified by design/characterization. table 9 dc characteristics (standard supply voltage range) (cont ? d) (operating conditions apply) 1) parameter symbol limit values unit test condition min. max. c161s electrical parameters data sheet 38 v1.0, 2003-11 table 10 dc characteristics (reduced supply voltage range) (operating conditions apply) 1) parameter symbol limit values unit test condition min. max. input low voltage (ttl, all except xtal1) v il sr -0.5 0.8 v ? input low voltage xtal1 v il2 sr -0.5 0.3 v dd v ? input high voltage (ttl, all except rstin and xtal1) v ih sr 1.8 v dd + 0.5 v ? input high voltage rstin (when operated as input) v ih1 sr 0.6 v dd v dd + 0.5 v ? input high voltage xtal1 v ih2 sr 0.7 v dd v dd + 0.5 v ? output low voltage (port0, port1, port 4, ale, rd , wr , bhe , rstout , rstin 2) ) v ol cc ? 0.45 v i ol = 1.6 ma output low voltage (all other outputs) v ol1 cc ? 0.45 v i ol = 1.0 ma output high voltage 3) (port0, port1, port 4, ale, rd , wr , bhe , rstout ) v oh cc 0.9 v dd ? v i oh = -0.5 ma output high voltage 3) (all other outputs) v oh1 cc 0.9 v dd ? v i oh = -0.25 ma input leakage current (port 5) i oz1 cc ? 200 na 0 v < v in < v dd input leakage current (all other) i oz2 cc ? 500 na 0.45 v < v in < v dd rstin inactive current 4) i rsth 5) ? -10 a v in = v ih1 rstin active current 4) i rstl 6) -100 ? a v in = v il rd /wr inactive current 7) i rwh 5) ? -10 a v out = 2.4 v rd /wr active current 7) i rwl 6) -500 ? a v out = v olmax ale inactive current 7) i alel 5) ? 20 a v out = v olmax ale active current 7) i aleh 6) 500 ? a v out = 2.4 v port 6 inactive current 7) i p6h 5) ? -10 a v out = 2.4 v port 6 active current 7) i p6l 6) -500 ? a v out = v ol1max c161s electrical parameters data sheet 39 v1.0, 2003-11 port0 configuration current 7) i p0h 5) ? -5 a v in = v ihmin i p0l 6) -100 ? a v in = v ilmax xtal1 input current i il cc ? 20 a0 v < v in < v dd pin capacitance 8) (digital inputs/outputs) c io cc ? 10 pf f = 1 mhz, t a = 25 c 1) keeping signal levels within the levels specified in this table, ensures operation without overload conditions. for signal levels outside these specifications also refer to the specification of the overload current i ov . 2) valid in bidirectional reset mode only. 3) this specification is not valid for outputs which are switched to open drain mode. in this case the respective output will float and the voltage results from the external circuitry. 4) these parameters describe the rstin pull-up, which equals a resistance of ca. 50 to 250 k ? . 5) the maximum current may be drawn while the respective signal line remains inactive. 6) the minimum current must be drawn in order to drive the respective signal line active. 7) this specification is only valid during reset and adapt mode. 8) not subject to production test, verified by design/characterization. table 10 dc characteristics (reduced supply voltage range) (cont ? d) (operating conditions apply) 1) parameter symbol limit values unit test condition min. max. c161s electrical parameters data sheet 40 v1.0, 2003-11 table 11 power consumption c161s (standard supply voltage range) (operating conditions apply) parameter symbol limit values unit test condition min. max. power supply current (active) with all peripherals active i dd5 ? 15 + 1.8 f cpu ma rstin = v il2 f cpu in [mhz] 1) idle mode supply current with all peripherals active i idx5 ? 3 + 0.6 f cpu ma rstin = v ih1 f cpu in [mhz] 1) idle mode supply current with all peripherals deactivated, pll off, sdd factor = 32 i ido5 2) ? 500 + 50 f osc arstin = v ih1 f osc in [mhz] 1) sleep and power down mode supply current with rtc running i pdr5 2) ? 200 + 25 f osc a v dd = v ddmax f osc in [mhz] 3) sleep and power down mode supply current with rtc disabled i pdo5 ? 50 a v dd = v ddmax 3) 1) the supply current is a function of the operating frequency. this dependency is illustrated in figure 8 . these parameters are tested at v ddmax and maximum cpu clock with all outputs disconnected and all inputs at v il or v ih . 2) this parameter is determined mainly by the current consumed by the oscillator (see figure 9 ). this current, however, is influenced by the external oscillator circuitry (crystal, capacitors). the values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. 3) this parameter is tested including leakage currents. all inputs (including pins configured as inputs) at 0 v to 0.1 v or at v dd - 0.1 v to v dd , v ref = 0 v, all outputs (including pins configured as outputs) disconnected. c161s electrical parameters data sheet 41 v1.0, 2003-11 table 12 power consumption c161s (reduced supply voltage range) (operating conditions apply) parameter symbol limit values unit test condition min. max. power supply current (active) with all peripherals active i dd3 ? 7 + 1.2 f cpu ma rstin = v il2 f cpu in [mhz] 1) idle mode supply current with all peripherals active i idx3 ? 1 + 0.4 f cpu ma rstin = v ih1 f cpu in [mhz] 1) idle mode supply current with all peripherals deactivated, pll off, sdd factor = 32 i ido3 2) ? 300 + 30 f osc arstin = v ih1 f osc in [mhz] 1) sleep and power down mode supply current with rtc running i pdr3 2) ? 100 + 10 f osc a v dd = v ddmax f osc in [mhz] 3) sleep and power down mode supply current with rtc disabled i pdo3 ? 30 a v dd = v ddmax 3) 1) the supply current is a function of the operating frequency. this dependency is illustrated in figure 8 . these parameters are tested at v ddmax and maximum cpu clock with all outputs disconnected and all inputs at v il or v ih . 2) this parameter is determined mainly by the current consumed by the oscillator (see figure 9 ). this current, however, is influenced by the external oscillator circuitry (crystal, capacitors). the values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. 3) this parameter is tested including leakage currents. all inputs (including pins configured as inputs) at 0 v to 0.1 v or at v dd - 0.1 v to v dd , v ref = 0 v, all outputs (including pins configured as outputs) disconnected. c161s electrical parameters data sheet 42 v1.0, 2003-11 figure 8 supply and idle current as a function of operating frequency i [ma] f cpu [mhz] 10 20 30 40 i dd5max i dd5typ i idx5typ 20 40 60 80 100 i dd3typ i idx3max i idx3typ i dd3max i idx5max c161s electrical parameters data sheet 43 v1.0, 2003-11 figure 9 sleep and power down supply current as a function of oscillator frequency i [ a] f osc [mhz] 10 20 30 40 i ido5max i ido5typ i pdr5max 500 1000 1500 2500 3000 i ido3typ i pdr3max i ido3max i pdomax c161s timing characteristics data sheet 44 v1.0, 2003-11 5 timing characteristics 5.1 definition of internal timing the internal operation of the c161s is controlled by the internal cpu clock f cpu . both edges of the cpu clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. the specification of the external timing (ac characteristics) therefore depends on the time between two consecutive edges of the cpu clock, called ? tcl ? (see figure 10 ). figure 10 generation mechanisms for the cpu clock the cpu clock signal f cpu can be generated from the oscillator clock signal f osc via different mechanisms. the duration of tcls and their variation (and also the derived external timing) depends on the used mechanism to generate f cpu . this influence must be regarded when calculating the timings for the c161s. note: the example for pll operation shown in figure 10 refers to a pll factor of 4. the used mechanism to generate the basic cpu clock is selected by bitfield clkcfg in register rp0h.7-5. upon a long hardware reset register rp0h is loaded with the logic mct04338 f osc f cpu phase locked loop operation tcl f osc f cpu direct clock drive f osc f cpu prescaler operation tcl tcl tcl tcl tcl c161s timing characteristics data sheet 45 v1.0, 2003-11 levels present on the upper half of port0 (p0h), i.e. bitfield clkcfg represents the logic levels on pins p0.15-13 (p0h.7-5). table 13 associates the combinations of these three bits with the respective clock generation mode. prescaler operation when prescaler operation is configured (clkcfg = 001 b ) the cpu clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. the frequency of f cpu is half the frequency of f osc and the high and low time of f cpu (i.e. the duration of an individual tcl) is defined by the period of the input clock f osc . the timings listed in the ac characteristics that refer to tcls therefore can be calculated using the period of f osc for any tcl. phase locked loop when pll operation is configured (via clkcfg) the on-chip phase locked loop is enabled and provides the cpu clock (see table 13 ). the pll multiplies the input frequency by the factor f which is selected via the combination of pins p0.15-13 (i.e. f cpu = f osc f ). with every f ? th transition of f osc the pll circuit synchronizes the cpu clock to the input clock. this synchronization is done smoothly, i.e. the cpu clock frequency does not change abruptly. due to this adaptation to the input clock the frequency of f cpu is constantly adjusted so it is locked to f osc . the slight variation causes a jitter of f cpu which also effects the duration of individual tcls. table 13 c161s clock generation modes clkcfg (p0h.7-5) cpu frequency f cpu = f osc f external clock input range 1) 1) the external clock input range refers to a cpu clock range of 10 ? 25 mhz (pll operation). if the on-chip oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 mhz to 16 mhz. notes 1 1 1 f osc 4 2.5 to 6.25 mhz default configuration 1 1 0 f osc 3 3.33 to 8.33 mhz ? 1 0 1 f osc 2 5 to 12.5 mhz ? 1 0 0 f osc 5 2 to 5 mhz ? 0 1 1 f osc 1 1 to 25 mhz direct drive 2) 2) the maximum frequency depends on the duty cycle of the external clock signal. 0 1 0 f osc 1.5 6.66 to 16.67 mhz ? 0 0 1 f osc / 2 2 to 50 mhz cpu clock via prescaler 0 0 0 f osc 2.5 4 to 10 mhz ? c161s timing characteristics data sheet 46 v1.0, 2003-11 the timings listed in the ac characteristics that refer to tcls therefore must be calculated using the minimum tcl that is possible under the respective circumstances. the actual minimum value for tcl depends on the jitter of the pll. as the pll is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one tcl is lower than for one single tcl (see formula and figure 11 ). for a period of n tcl the minimum value is computed using the corresponding deviation d n : ( n tcl) min = n tcl nom - d n , d n [ns] = (13.3 + n 6.3) / f cpu [mhz] (1) where n = number of consecutive tcls and 1 n 40. so for a period of 3 tcls @ 20 mhz (i.e. n = 3): d 3 = (13.3 + 3 6.3) / 20 = 1.61 ns, and (3tcl) min = 3tcl nom - 1.61 ns = 73.39 ns (@ f cpu = 20 mhz). this is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. for all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the pll jitter is negligible. note: for all periods longer than 40 tcl the n = 40 value can be used (see figure 11 ). figure 11 approximated maximum accumulated pll jitter mcd04455 n max. jitter d n ? ?0 ?0 ?0 ns ?6.5 110 20 40 this approximated formula is valid for 1 n 40 and 10 mhz f cpu 25 mhz. 10 mhz 16 mhz 20 mhz 25 mhz 30 < ? < ? < ? < ? c161s timing characteristics data sheet 47 v1.0, 2003-11 direct drive when direct drive is configured (clkcfg = 011 b ) the on-chip phase locked loop is disabled and the cpu clock is directly driven from the internal oscillator with the input clock signal. the frequency of f cpu directly follows the frequency of f osc so the high and low time of f cpu (i.e. the duration of an individual tcl) is defined by the duty cycle of the input clock f osc . the timings listed below that refer to tcls therefore must be calculated using the minimum tcl that is possible under the respective circumstances. this minimum value can be calculated via the following formula: tcl min = 1/ f osc dc min (dc = duty cycle) (2) for two consecutive tcls the deviation caused by the duty cycle of f osc is compensated so the duration of 2tcl is always 1/ f osc . the minimum value tcl min therefore has to be used only once for timings that require an odd number of tcls (1, 3, ? ). timings that require an even number of tcls (2, 4, ? ) may use the formula 2tcl = 1/ f osc . c161s timing characteristics data sheet 48 v1.0, 2003-11 5.2 external clock drive xtal1 figure 12 external clock drive xtal1 note: if the on-chip oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 mhz to 16 mhz. it is strongly recommended to measure the oscillation allowance (or margin) in the final target system (layout) to determine the optimum parameters for the oscillator operation. please refer to the limits specified by the crystal supplier. when driven by an external clock signal it will accept the specified frequency range. operation at lower input frequencies is possible but is verified by design only (not tested in production). table 14 external clock drive xtal1 (operating conditions apply) parameter symbol direct drive 1:1 prescaler 2:1 pll 1:n unit min. max. min. max. min. max. oscillator period t osc sr 40 ? 20 ? 60 1) 1) the minimum and maximum oscillator periods for pll operation depend on the selected cpu clock generation mode. please see respective table above. 500 1) ns high time 2) 2) the clock input signal must reach the defined levels v il2 and v ih2 . t 1 sr 20 3) 3) the minimum high and low time refers to a duty cycle of 50%. the maximum operating frequency ( f cpu ) in direct drive mode depends on the duty cycle of the clock input signal. ? 5 ? 10 ? ns low time 2) t 2 sr 20 3) ? 5 ? 10 ? ns rise time 2) t 3 sr ? 8 ? 5 ? 10 ns fall time 2) t 4 sr ? 8 ? 5 ? 10 ns mct02534 3 t 4 t v ih2 v il v dd 0.5 1 t 2 t osc t c161s timing characteristics data sheet 49 v1.0, 2003-11 5.3 testing waveforms figure 13 input output waveforms figure 14 float waveforms mca04414 2.4 v 0.45 v 1.8 v 0.8 v 1.8 v 0.8 v test points ac inputs during testing are driven at 2.4 v for a logic 1 ? and 0.45 v for a logic 0 ? . timing measurements are made at ih v min for a logic 1 ? and v il max for a logic 0 ? . ? ? ? ? mca00763 - 0.1 v + 0.1 v + 0.1 v - 0.1 v reference for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs, but begins to float when a 100 mv change from the loaded oh v timing points load v v load oh v v ol / v ol level occurs ( i oh ol i / = 20 ma). c161s timing characteristics data sheet 50 v1.0, 2003-11 memory cycle variables the timing tables below use three variables which are derived from the busconx registers and represent the special characteristics of the programmed memory cycle. table 15 describes, how these variables are to be computed. note: please respect the maximum operating frequency of the respective derivative. 5.4 ac characteristics table 15 memory cycle variables description symbol values ale extension t a tcl c161s timing characteristics data sheet 51 v1.0, 2003-11 rd , wr low time (with rw-delay) t 12 cc 30 + t c ? 2tcl - 10 + t c ? ns rd , wr low time (no rw-delay) t 13 cc 50 + t c ? 3tcl - 10 + t c ? ns rd to valid data in (with rw-delay) t 14 sr ? 20 + t c ? 2tcl - 20 + t c ns rd to valid data in (no rw-delay) t 15 sr ? 40 + t c ? 3tcl - 20 + t c ns ale low to valid data in t 16 sr ? 40 + t a + t c ? 3tcl - 20 + t a + t c ns address to valid data in t 17 sr ? 50 + 2 t a + t c ? 4tcl - 30 + 2 t a + t c ns data hold after rd rising edge t 18 sr 0 ? 0 ? ns data float after rd t 19 sr ? 26 + t f ? 2tcl - 14 + t f ns data valid to wr t 22 cc 20 + t c ? 2tcl - 20 + t c ? ns data hold after wr t 23 cc 26 + t f ? 2tcl - 14 + t f ? ns ale rising edge after rd , wr t 25 cc 26 + t f ? 2tcl - 14 + t f ? ns address hold after rd , wr t 27 cc 26 + t f ? 2tcl - 14 + t f ? ns ale falling edge to cs 1) t 38 cc -4 - t a 10 - t a -4 - t a 10 - t a ns cs low to valid data in 1) t 39 sr ? 40 + t c + 2 t a ? 3tcl - 20 + t c + 2 t a ns cs hold after rd , wr 1) t 40 cc 46 + t f ? 3tcl - 14 + t f ? ns table 16 multiplexed bus (standard supply voltage range) (cont ? d) (operating conditions apply) ale cycle time = 6 tcl + 2 t a + t c + t f (120 ns at 25 mhz cpu clock without waitstates) parameter symbol max. cpu clock = 25 mhz variable cpu clock 1 / 2tcl = 1 to 25 mhz unit min. max. min. max. c161s timing characteristics data sheet 52 v1.0, 2003-11 ale fall. edge to rdcs , wrcs (with rw delay) t 42 cc 16 + t a ? tcl - 4 + t a ? ns ale fall. edge to rdcs , wrcs (no rw delay) t 43 cc -4 + t a ? -4 + t a ? ns address float after rdcs , wrcs (with rw delay) t 44 cc ? 0 ? 0ns address float after rdcs , wrcs (no rw delay) t 45 cc ? 20 ? tcl ns rdcs to valid data in (with rw delay) t 46 sr ? 16 + t c ? 2tcl - 24 + t c ns rdcs to valid data in (no rw delay) t 47 sr ? 36 + t c ? 3tcl - 24 + t c ns rdcs , wrcs low time (with rw delay) t 48 cc 30 + t c ? 2tcl - 10 + t c ? ns rdcs , wrcs low time (no rw delay) t 49 cc 50 + t c ? 3tcl - 10 + t c ? ns data valid to wrcs t 50 cc 26 + t c ? 2tcl - 14 + t c ? ns data hold after rdcs t 51 sr 0 ? 0 ? ns data float after rdcs t 52 sr ? 20 + t f ? 2tcl - 20 + t f ns address hold after rdcs , wrcs t 54 cc 20 + t f ? 2tcl - 20 + t f ? ns data hold after wrcs t 56 cc 20 + t f ? 2tcl - 20 + t f ? ns 1) these parameters refer to the latched chip select signals (csxl ). the early chip select signals (csxe ) are specified together with the address and signal bhe (see figures below). table 16 multiplexed bus (standard supply voltage range) (cont ? d) (operating conditions apply) ale cycle time = 6 tcl + 2 t a + t c + t f (120 ns at 25 mhz cpu clock without waitstates) parameter symbol max. cpu clock = 25 mhz variable cpu clock 1 / 2tcl = 1 to 25 mhz unit min. max. min. max. c161s timing characteristics data sheet 53 v1.0, 2003-11 table 17 multiplexed bus (reduced supply voltage range) (operating conditions apply) ale cycle time = 6 tcl + 2 t a + t c + t f (150 ns at 20 mhz cpu clock without waitstates) parameter symbol max. cpu clock = 20 mhz variable cpu clock 1 / 2tcl = 1 to 20 mhz unit min. max. min. max. ale high time t 5 cc 11 + t a ? tcl - 14 + t a ? ns address setup to ale t 6 cc 5 + t a ? tcl - 20 + t a ? ns address hold after ale t 7 cc 15 + t a ? tcl - 10 + t a ? ns ale falling edge to rd , wr (with rw-delay) t 8 cc 15 + t a ? tcl - 10 + t a ? ns ale falling edge to rd , wr (no rw-delay) t 9 cc -10 + t a ? -10 + t a ? ns address float after rd , wr (with rw-delay) t 10 cc ? 6 ? 6ns address float after rd , wr (no rw-delay) t 11 cc ? 31 ? tcl + 6 ns rd , wr low time (with rw-delay) t 12 cc 34 + t c ? 2tcl - 16 + t c ? ns rd , wr low time (no rw-delay) t 13 cc 59 + t c ? 3tcl - 16 + t c ? ns rd to valid data in (with rw-delay) t 14 sr ? 22 + t c ? 2tcl - 28 + t c ns rd to valid data in (no rw-delay) t 15 sr ? 47 + t c ? 3tcl - 28 + t c ns ale low to valid data in t 16 sr ? 45 + t a + t c ? 3tcl - 30 + t a + t c ns address to valid data in t 17 sr ? 57 + 2 t a + t c ? 4tcl - 43 + 2 t a + t c ns data hold after rd rising edge t 18 sr 0 ? 0 ? ns data float after rd t 19 sr ? 36 + t f ? 2tcl - 14 + t f ns c161s timing characteristics data sheet 54 v1.0, 2003-11 data valid to wr t 22 cc 24 + t c ? 2tcl - 26 + t c ? ns data hold after wr t 23 cc 36 + t f ? 2tcl - 14 + t f ? ns ale rising edge after rd , wr t 25 cc 36 + t f ? 2tcl - 14 + t f ? ns address hold after rd , wr t 27 cc 36 + t f ? 2tcl - 14 + t f ? ns ale falling edge to cs 1) t 38 cc -8 - t a 10 - t a -8 - t a 10 - t a ns cs low to valid data in 1) t 39 sr ? 47 + t c + 2 t a ? 3tcl - 28 + t c + 2 t a ns cs hold after rd , wr 1) t 40 cc 57 + t f ? 3tcl - 18 + t f ? ns ale fall. edge to rdcs , wrcs (with rw delay) t 42 cc 19 + t a ? tcl - 6 + t a ? ns ale fall. edge to rdcs , wrcs (no rw delay) t 43 cc -6 + t a ? -6 + t a ? ns address float after rdcs , wrcs (with rw delay) t 44 cc ? 0 ? 0ns address float after rdcs , wrcs (no rw delay) t 45 cc ? 25 ? tcl ns rdcs to valid data in (with rw delay) t 46 sr ? 20 + t c ? 2tcl - 30 + t c ns rdcs to valid data in (no rw delay) t 47 sr ? 45 + t c ? 3tcl - 30 + t c ns rdcs , wrcs low time (with rw delay) t 48 cc 38 + t c ? 2tcl - 12 + t c ? ns rdcs , wrcs low time (no rw delay) t 49 cc 63 + t c ? 3tcl - 12 + t c ? ns table 17 multiplexed bus (reduced supply voltage range) (cont ? d) (operating conditions apply) ale cycle time = 6 tcl + 2 t a + t c + t f (150 ns at 20 mhz cpu clock without waitstates) parameter symbol max. cpu clock = 20 mhz variable cpu clock 1 / 2tcl = 1 to 20 mhz unit min. max. min. max. c161s timing characteristics data sheet 55 v1.0, 2003-11 data valid to wrcs t 50 cc 28 + t c ? 2tcl - 22 + t c ? ns data hold after rdcs t 51 sr 0 ? 0 ? ns data float after rdcs t 52 sr ? 30 + t f ? 2tcl - 20 + t f ns address hold after rdcs , wrcs t 54 cc 30 + t f ? 2tcl - 20 + t f ? ns data hold after wrcs t 56 cc 30 + t f ? 2tcl - 20 + t f ? ns 1) these parameters refer to the latched chip select signals (csxl ). the early chip select signals (csxe ) are specified together with the address and signal bhe (see figures below). table 17 multiplexed bus (reduced supply voltage range) (cont ? d) (operating conditions apply) ale cycle time = 6 tcl + 2 t a + t c + t f (150 ns at 20 mhz cpu clock without waitstates) parameter symbol max. cpu clock = 20 mhz variable cpu clock 1 / 2tcl = 1 to 20 mhz unit min. max. min. max. c161s timing characteristics data sheet 56 v1.0, 2003-11 figure 15 external memory cycle: multiplexed bus, with read/write delay, normal ale a23-a16 (a15-a8) bhe , csxe data in data out address address t 38 t 44 t 10 address ale csxl bus read cycle rd rdcsx bus write cycle wr , wrl , wrh wrcsx t 5 t 16 t 17 t 6 t 7 t 39 t 40 t 25 t 27 t 18 t 19 t 14 t 46 t 12 t 48 t 10 t 22 t 23 t 44 t 12 t 48 t 8 t 42 t 42 t 8 t 50 t 51 t 54 t 52 t 56 c161s timing characteristics data sheet 57 v1.0, 2003-11 figure 16 external memory cycle: multiplexed bus, with read/write delay, extended ale data out address data in address t 38 t 44 t 10 address ale csxl a23-a16 (a15-a8) bhe , csxe bus read cycle rd rdcsx bus write cycle wr , wrl , wrh wrcsx t 5 t 16 t 17 t 6 t 7 t 39 t 40 t 25 t 27 t 18 t 19 t 14 t 46 t 12 t 48 t 10 t 22 t 23 t 44 t 12 t 48 t 8 t 42 t 42 t 8 t 50 t 51 t 54 t 52 t 56 c161s timing characteristics data sheet 58 v1.0, 2003-11 figure 17 external memory cycle: multiplexed bus, no read/write delay, normal ale data out address address data in t 38 address ale csxl a23-a16 (a15-a8) bhe , csxe bus read cycle rd rdcsx bus write cycle wr , wrl , wrh wrcsx t 5 t 16 t 17 t 6 t 7 t 39 t 40 t 25 t 27 t 18 t 19 t 15 t 47 t 13 t 49 t 22 t 23 t 13 t 49 t 9 t 43 t 43 t 9 t 11 t 45 t 11 t 45 t 50 t 51 t 54 t 52 t 56 c161s timing characteristics data sheet 59 v1.0, 2003-11 figure 18 external memory cycle: multiplexed bus, no read/write delay, extended ale data out address data in address t 38 address ale csxl a23-a16 (a15-a8) bhe , csxe bus read cycle rd rdcsx bus write cycle wr , wrl , wrh wrcsx t 5 t 16 t 17 t 6 t 7 t 39 t 40 t 25 t 27 t 18 t 19 t 15 t 47 t 13 t 49 t 22 t 23 t 13 t 49 t 9 t 43 t 43 t 9 t 11 t 45 t 11 t 45 t 50 t 51 t 54 t 52 t 56 c161s timing characteristics data sheet 60 v1.0, 2003-11 table 18 demultiplexed bus (standard supply voltage range) (operating conditions apply) ale cycle time = 4 tcl + 2 t a + t c + t f (80 ns at 25 mhz cpu clock without waitstates) parameter symbol max. cpu clock = 25 mhz variable cpu clock 1 / 2tcl = 1 to 25 mhz unit min. max. min. max. ale high time t 5 cc 10 + t a ? tcl - 10 + t a ? ns address setup to ale t 6 cc 4 + t a ? tcl - 16 + t a ? ns ale falling edge to rd , wr (with rw-delay) t 8 cc 10 + t a ? tcl - 10 + t a ? ns ale falling edge to rd , wr (no rw-delay) t 9 cc -10 + t a ? -10 + t a ? ns rd , wr low time (with rw-delay) t 12 cc 30 + t c ? 2tcl - 10 + t c ? ns rd , wr low time (no rw-delay) t 13 cc 50 + t c ? 3tcl - 10 + t c ? ns rd to valid data in (with rw-delay) t 14 sr ? 20 + t c ? 2tcl - 20 + t c ns rd to valid data in (no rw-delay) t 15 sr ? 40 + t c ? 3tcl - 20 + t c ns ale low to valid data in t 16 sr ? 40 + t a + t c ? 3tcl - 20 + t a + t c ns address to valid data in t 17 sr ? 50 + 2 t a + t c ? 4tcl - 30 + 2 t a + t c ns data hold after rd rising edge t 18 sr 0 ? 0 ? ns data float after rd rising edge (with rw-delay 1) ) t 20 sr ? 26 + 2 t a + t f 1) ? 2tcl - 14 + 22 t a + t f 1) ns data float after rd rising edge (no rw-delay 1) ) t 21 sr ? 10 + 2 t a + t f 1) ? tcl - 10 + 22 t a + t f 1) ns data valid to wr t 22 cc 20 + t c ? 2tcl - 20 + t c ? ns c161s timing characteristics data sheet 61 v1.0, 2003-11 data hold after wr t 24 cc 10 + t f ? tcl - 10 + t f ? ns ale rising edge after rd , wr t 26 cc -10 + t f ? -10 + t f ? ns address hold after wr 2) t 28 cc 0 + t f ? 0 + t f ? ns ale falling edge to cs 3) t 38 cc -4 - t a 10 - t a -4 - t a 10 - t a ns cs low to valid data in 3) t 39 sr ? 40 + t c + 2 t a ? 3tcl - 20 + t c + 2 t a ns cs hold after rd , wr 3) t 41 cc 6 + t f ? tcl - 14 + t f ? ns ale falling edge to rdcs , wrcs (with rw-delay) t 42 cc 16 + t a ? tcl - 4 + t a ? ns ale falling edge to rdcs , wrcs (no rw-delay) t 43 cc -4 + t a ? -4 + t a ? ns rdcs to valid data in (with rw-delay) t 46 sr ? 16 + t c ? 2tcl - 24 + t c ns rdcs to valid data in (no rw-delay) t 47 sr ? 36 + t c ? 3tcl - 24 + t c ns rdcs , wrcs low time (with rw-delay) t 48 cc 30 + t c ? 2tcl - 10 + t c ? ns rdcs , wrcs low time (no rw-delay) t 49 cc 50 + t c ? 3tcl - 10 + t c ? ns data valid to wrcs t 50 cc 26 + t c ? 2tcl - 14 + t c ? ns data hold after rdcs t 51 sr 0 ? 0 ? ns data float after rdcs (with rw-delay) 1) t 53 sr ? 20 + t f ? 2tcl - 20 + 2 t a + t f 1) ns table 18 demultiplexed bus (standard supply voltage range) (cont ? d) (operating conditions apply) ale cycle time = 4 tcl + 2 t a + t c + t f (80 ns at 25 mhz cpu clock without waitstates) parameter symbol max. cpu clock = 25 mhz variable cpu clock 1 / 2tcl = 1 to 25 mhz unit min. max. min. max. c161s timing characteristics data sheet 62 v1.0, 2003-11 data float after rdcs (no rw-delay) 1) t 68 sr ? 0 + t f ? tcl - 20 + 2 t a + t f 1) ns address hold after rdcs , wrcs t 55 cc -6 + t f ? -6 + t f ? ns data hold after wrcs t 57 cc 6 + t f ? tcl - 14 + t f ? ns 1) rw-delay and t a refer to the next following bus cycle (including an access to an on-chip x-peripheral). 2) read data are latched with the same clock edge that triggers the address change and the rising rd edge. therefore address changes before the end of rd have no impact on read cycles. 3) these parameters refer to the latched chip select signals (csxl ). the early chip select signals (csxe ) are specified together with the address and signal bhe (see figures below). table 18 demultiplexed bus (standard supply voltage range) (cont ? d) (operating conditions apply) ale cycle time = 4 tcl + 2 t a + t c + t f (80 ns at 25 mhz cpu clock without waitstates) parameter symbol max. cpu clock = 25 mhz variable cpu clock 1 / 2tcl = 1 to 25 mhz unit min. max. min. max. c161s timing characteristics data sheet 63 v1.0, 2003-11 table 19 demultiplexed bus (reduced supply voltage range) (operating conditions apply) ale cycle time = 4 tcl + 2 t a + t c + t f (100 ns at 20 mhz cpu clock without waitstates) parameter symbol max. cpu clock = 20 mhz variable cpu clock 1 / 2tcl = 1 to 20 mhz unit min. max. min. max. ale high time t 5 cc 11 + t a ? tcl - 14 + t a ? ns address setup to ale t 6 cc 5 + t a ? tcl - 20 + t a ? ns ale falling edge to rd , wr (with rw-delay) t 8 cc 15 + t a ? tcl - 10 + t a ? ns ale falling edge to rd , wr (no rw-delay) t 9 cc -10 + t a ? -10 + t a ? ns rd , wr low time (with rw-delay) t 12 cc 34 + t c ? 2tcl - 16 + t c ? ns rd , wr low time (no rw-delay) t 13 cc 59 + t c ? 3tcl - 16 + t c ? ns rd to valid data in (with rw-delay) t 14 sr ? 22 + t c ? 2tcl - 28 + t c ns rd to valid data in (no rw-delay) t 15 sr ? 47 + t c ? 3tcl - 28 + t c ns ale low to valid data in t 16 sr ? 45 + t a + t c ? 3tcl - 30 + t a + t c ns address to valid data in t 17 sr ? 57 + 2 t a + t c ? 4tcl - 43 + 2 t a + t c ns data hold after rd rising edge t 18 sr 0 ? 0 ? ns data float after rd rising edge (with rw-delay 1) ) t 20 sr ? 36 + 2 t a + t f 1) ? 2tcl - 14 + 22 t a + t f 1) ns data float after rd rising edge (no rw-delay 1) ) t 21 sr ? 15 + 2 t a + t f 1) ? tcl - 10 + 22 t a + t f 1) ns data valid to wr t 22 cc 24 + t c ? 2tcl - 26 + t c ? ns c161s timing characteristics data sheet 64 v1.0, 2003-11 data hold after wr t 24 cc 15 + t f ? tcl - 10 + t f ? ns ale rising edge after rd , wr t 26 cc -12 + t f ? -12 + t f ? ns address hold after wr 2) t 28 cc 0 + t f ? 0 + t f ? ns ale falling edge to cs 3) t 38 cc -8 - t a 10 - t a -8 - t a 10 - t a ns cs low to valid data in 3) t 39 sr ? 47 + t c + 2 t a ? 3tcl - 28 + t c + 2 t a ns cs hold after rd , wr 3) t 41 cc 9 + t f ? tcl - 16 + t f ? ns ale falling edge to rdcs , wrcs (with rw-delay) t 42 cc 19 + t a ? tcl - 6 + t a ? ns ale falling edge to rdcs , wrcs (no rw-delay) t 43 cc -6 + t a ? -6 + t a ? ns rdcs to valid data in (with rw-delay) t 46 sr ? 20 + t c ? 2tcl - 30 + t c ns rdcs to valid data in (no rw-delay) t 47 sr ? 45 + t c ? 3tcl - 30 + t c ns rdcs , wrcs low time (with rw-delay) t 48 cc 38 + t c ? 2tcl - 12 + t c ? ns rdcs , wrcs low time (no rw-delay) t 49 cc 63 + t c ? 3tcl - 12 + t c ? ns data valid to wrcs t 50 cc 28 + t c ? 2tcl - 22 + t c ? ns data hold after rdcs t 51 sr 0 ? 0 ? ns data float after rdcs (with rw-delay) 1) t 53 sr ? 30 + t f ? 2tcl - 20 + 2 t a + t f 1) ns table 19 demultiplexed bus (reduced supply voltage range) (cont ? d) (operating conditions apply) ale cycle time = 4 tcl + 2 t a + t c + t f (100 ns at 20 mhz cpu clock without waitstates) parameter symbol max. cpu clock = 20 mhz variable cpu clock 1 / 2tcl = 1 to 20 mhz unit min. max. min. max. c161s timing characteristics data sheet 65 v1.0, 2003-11 data float after rdcs (no rw-delay) 1) t 68 sr ? 5 + t f ? tcl - 20 + 2 t a + t f 1) ns address hold after rdcs , wrcs t 55 cc -16 + t f ? -16 + t f ? ns data hold after wrcs t 57 cc 9 + t f ? tcl - 16 + t f ? ns 1) rw-delay and t a refer to the next following bus cycle (including an access to an on-chip x-peripheral). 2) read data are latched with the same clock edge that triggers the address change and the rising rd edge. therefore address changes before the end of rd have no impact on read cycles. 3) these parameters refer to the latched chip select signals (csxl ). the early chip select signals (csxe ) are specified together with the address and signal bhe (see figures below). table 19 demultiplexed bus (reduced supply voltage range) (cont ? d) (operating conditions apply) ale cycle time = 4 tcl + 2 t a + t c + t f (100 ns at 20 mhz cpu clock without waitstates) parameter symbol max. cpu clock = 20 mhz variable cpu clock 1 / 2tcl = 1 to 20 mhz unit min. max. min. max. c161s timing characteristics data sheet 66 v1.0, 2003-11 figure 19 external memory cycle: demultiplexed bus, with read/write delay, normal ale data out data in t 38 address ale csxl a23-a16 a15-a0 bhe , csxe bus (d15-d8) d7-d0 read cycle rd rdcsx write cycle wrcsx t 5 t 16 t 17 t 6 t 39 t 41 t 26 t 28 t 18 t 20 t 14 t 46 t 12 t 48 t 22 t 24 t 12 t 48 t 8 t 42 t 42 t 8 t 50 t 51 t 55 t 53 t 57 bus (d15-d8) d7-d0 wr , wrl , wrh c161s timing characteristics data sheet 67 v1.0, 2003-11 figure 20 external memory cycle: demultiplexed bus, with read/write delay, extended ale data out data in t 38 address ale csxl a23-a16 a15-a0 bhe , csxe read cycle rd rdcsx write cycle wrcsx t 5 t 16 t 17 t 6 t 39 t 41 t 26 t 28 t 18 t 20 t 14 t 46 t 12 t 48 t 22 t 24 t 12 t 48 t 8 t 42 t 42 t 8 t 50 t 51 t 55 t 53 t 57 bus (d15-d8) d7-d0 bus (d15-d8) d7-d0 wr , wrl , wrh c161s timing characteristics data sheet 68 v1.0, 2003-11 figure 21 external memory cycle: demultiplexed bus, no read/write delay, normal ale data out data in t 38 address ale csxl a23-a16 a15-a0 bhe , csxe read cycle rd rdcsx write cycle wrcsx t 5 t 16 t 17 t 6 t 39 t 41 t 26 t 28 t 18 t 21 t 15 t 47 t 13 t 49 t 22 t 24 t 13 t 49 t 9 t 43 t 43 t 9 t 50 t 51 t 55 t 68 t 57 bus (d15-d8) d7-d0 bus (d15-d8) d7-d0 wr , wrl , wrh c161s timing characteristics data sheet 69 v1.0, 2003-11 figure 22 external memory cycle: demultiplexed bus, no read/write delay, extended ale data out data in t 38 address ale csxl a23-a16 a15-a0 bhe , csxe read cycle rd rdcsx write cycle wr , wrl , wrh wrcsx t 5 t 16 t 17 t 6 t 39 t 41 t 26 t 28 t 18 t 21 t 15 t 47 t 13 t 49 t 22 t 24 t 13 t 49 t 9 t 43 t 43 t 9 t 50 t 51 t 55 t 68 t 57 bus (d15-d8) d7-d0 bus (d15-d8) d7-d0 c161s package outlines data sheet 70 v1.0, 2003-11 6 package outlines figure 23 p-mqfp-80-7 (plastic metric quad flat package) does not include plastic or metal protrusion of 0.25 max. per side index marking 0.6 x 45? 80 1 a 0.65 0.3 ?.08 14 1) 17.2 d b 0.2 0.2 a-b 0.12 12.35 m 0.25 min. c d c 80x 2 +0.1 -0.05 4x d d a-b a-b h 4x 2.45 max. 0.1 h 0.88 ?.15 0.15 +0.08 -0.02 max. 7? 17.2 14 1) 1) gpm05249 you can find all of our packages, sorts of packing and others in our infineon internet page ?roducts? http://www.infineon.com/products . dimensions in mm smd = surface mounted device www.infineon.com published by infineon technologies ag |
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